The present invention relates to semiconductor memory devices.
In a semiconductor memory device, such as a dynamic random access memory (DRAM) device, a sense amplifier is provided to sense a small potential difference between a reference voltage and voltage on an active bitline connected to a memory storage cell in a memory array. The sense amplifier amplifies the small difference from which a binary state is determined for the memory storage cell.
In a typical DRAM, the sense amplifier is shared by first and second memory array segments to sense voltage on bitlines to either one memory array segment or the other memory array segment, but never sensing from both memory array segments at the same time. To this end, a first multiplexer is provided that connects a sense node pair of the sense amplifier to, and disconnects the sense node pair from, the first memory array segment. A second multiplexer is provided that connects the sense node pair of the sense amplifier to, and disconnects the sense node pair from, the second memory array segment. Control logic is provided in the memory device to generate multiplexer control signals that control the state of the first and second multiplexers depending on the state of selection signals. The selection signals are derived from control and address signals in order to select the appropriate memory array segments for access.
When a memory array segment associated with a sense amplifier is unselected, the sense amplifier is allowed to stay connected to the memory array segment in order to undergo a so-called precharging sequence that allows the bitline pair connected to the memory array segment (and to the sense amplifier via the multiplexer) to precharge and equalize the voltage on sense nodes of the sense amplifier. This precharging sequence brings the sense nodes of the sense amplifier to a sufficient and equalized voltage so that it is ready for an access to a memory array segment at the next selection cycle. The term “equalization” used in the art to refer to bringing a bitlines in a bitline pair and/or sense nodes in a sense node pair of a sense amplifier to a desired and equal voltage.
A technique has been developed to reduce leakage current associated with a wordline to bitline short-circuit condition in a memory array cell by disconnecting the sense amplifier sense nodes from that memory array segment during periods when it is unselected in order to isolate the sense amplifier from the memory array segment containing the short-circuit condition. A consequence of this isolation technique is that the effectiveness of the precharging sequence is reduced because the sense amplifier is immediately disconnected from the memory array segment that has the short circuit condition when the memory array segment state is transitioning from a selected state to an unselected state. Therefore, the sense amplifier sense nodes are not given sufficient time to be precharged and equalized by the bitline pair associated with that memory array segment. Consequently, the sense node equalization is slower and exhibits a DC offset.
Thus, a technique is needed to improve sense amplifier sense node equalization during transitions from a selected state of a memory array segment to an unselected state when the sense amplifier is to be isolated from the memory array segment.